`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:46:09 07/16/2017
// Design Name:   id_fsm
// Module Name:   Q:/p/MD/id_fsm_tb.v
// Project Name:  MD
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: id_fsm
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module id_fsm_tb;

	// Inputs
	reg [7:0] char;
	reg clk;
	reg en;
	reg [127*8-1:0] teststr;
	

	
	integer i,j;

	// Outputs
	wire out;

	// Instantiate the Unit Under Test (UUT)
	id_fsm uut (
		.char(char), 
		.clk(clk), 
		.out(out)
	);

	initial begin
		teststr = "110fuckyouleatherman 8 shit;";
		// Initialize Inputs
		char = 0;
		clk = 0;
		en = 0;

		// Wait 100 ns for global reset to finish
/*		#100;
		char = "a";
		#10;
		char = "_";
		#10;
		char = "8";
		#10;
		char = ".";
		#10;
      for (i=60;i>=0;i=i-1) begin
			for (j=0;j<8;j=j+1) begin
				char[j] = teststr[8*i+j];
			end
			#10;
		end
*/
		// Add stimulus here
		char = "I";#10;

		char = " ";#10;

		char = "t";#10;

		char = "h";#10;

		char = "i";#10;

		char = "n";#10;

		char = "k";#10;

		char = " ";#10;

		char = "t";#10;

		char = "h";#10;

		char = "i";#10;

		char = "s";#10;

		char = " ";#10;

		char = "q";#10;

		char = "u";#10;

		char = "e";#10;

		char = "s";#10;

		char = "t";#10;

		char = "i";#10;

		char = "o";#10;

		char = "n";#10;

		char = " ";#10;

		char = "i";#10;

		char = "s";#10;

		char = " ";#10;

		char = "2";#10;

		char = " ";#10;

		char = "e";#10;

		char = "a";#10;

		char = "s";#10;

		char = "y";#10;

		char = ".";#10;
	end
	always #5 clk = ~clk; 
 
endmodule

